1. Technical Field
The present invention relates to chip testing circuits, and more specifically to a shared built in self testing (BIST) device for testing multiple memories of various characteristics, such as various addressable sizes, various operating speeds, and various data widths.
2. Description of the Related Art
Technological advancements have made it possible to integrate more and more components, even a complete system, into a single chip, called system-on-chip (SOC). Embedded memories are the most common cores in SOC design and are considered to be the vital microelectronic components of a digital logic system.
Several conventional methods are available for testing integrated memory blocks. One conventional method available is to pin out either directly or through multiplexers, the address, control and data pins of the memory. However, the pin count required to test a device by this method can be larger than the number of pins available. Also, for each memory multiplexed, additional logic will have to be introduced, which results in a slower input/output propagation time, which in turn can affect the performance.
Thus, testing embedded memories is a challenge, since testing memory cores is much more difficult than testing commodity memories due to the limitation in available pins that can be used to access the cores.
Another conventional method is the self test method. A self test refers to the presence of testing circuits on a component containing the circuits to be tested. The self test can be accomplished with testing circuits integrated into the circuits to be tested, known as the on-chip testing method, or with the testing circuits located externally on the component, known as the off-chip testing method. On-chip testing is faster as compared to off-chip testing because of the closeness to the circuits being tested.
A conventional self test method is the use of Built-In-Self-Test (BIST) circuits for testing integrated memories. A BIST controller is used to automatically verify functionality of individual blocks of memory. The BIST is considered a good alternative solution to expensive memory testers. The BIST not only provides at-speed testing of memory cores but also decreases the test pattern development time as fewer test patterns are required.
However, BIST technology consumes larger area. BIST consumes 4% to 8% area of the memory and this can increase to more than 150% for smaller memories. The area of the BIST increases with algorithm length and complexity.
FIG. 1 illustrates a conventional BIST method, wherein, each memory instance has a dedicated BIST to test it. So, for a chip containing 70% of area as memory, dedicated BISTs can occupy an unacceptable amount of valuable chip area.
BIST have been shared between memories of same words and bits but these memories should be present in close proximity in the chip. If the memories are working at high frequencies, then testing memories at-speed with a shared BIST becomes impossible.
U.S. Pat. No. 4,903,266 discloses a system and method for on chip self testing of a memory circuit. In this method, the testing is done by using a random pattern generator based upon a primitive polynomial and including a linear feedback shift register having at least one stage in addition to the number of address lines required for addressing the memory. The random pattern generator is capable of cycling through all memory addresses. During each random pattern generator cycles, known data is written or read out of each memory cell. By this method, both possible states of each memory cell can be tested as means for writing and reading the complement of a data during random pattern generator cycles are included. The output is routed to a multiple input signature register and a data signature is generated. The data signature is compared with an expected data signature. This method also provides for a logic circuit testing using a known level sensitive scan design technique. The test output data is provided to a multiple input signature register. A single data signature is then generated, which is indicative of a good or a bad status of both the logic and memory circuits.
U.S. Pat. No. 5,535,164 discloses a system and method for testing a multiplicity of memories of different sizes, types and characteristics using a single built in self test (BIST). The system uses a state machine to select and generate all patterns required for testing all the memories on the chip and impressing all the data, including expected data and the address information on all of the memories simultaneously. The BIST generates unique control signals for various memories and impresses the control signals on the various memories. The BIST selectively asserts the various control signals to write data and to read and capture failure information only to or from those memories, whose unique control signals are asserted. The control signals instruct those memories that do not use particular sequence of inputs or any portion of a given sequence of inputs to ignore such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory and capture error information for that particular memory.
U.S. Pat. No. 5,617,531 discloses a method for internally testing a plurality of embedded memories of a data processor. In this method a data processor has a single test controller. The test controller has a test pattern generator and a memory verification element. The test pattern generated by the test pattern generator is transmitted through a data bus of the data processor to each embedded memory of the plurality of embedded memories through a second storage device. A data read for the plurality of embedded memories is stored in a first storage device. The data from the first storage device is selectively accessed by the memory verification element through the bus. A bit or more than one bit is used to determine whether the memories are operating in an error free manner.
U.S. Pat. No. 6,321,320 discloses a system and method for at-speed access, testing, characterization and monitoring of on-chip memory arrays using a BIST engine independent of other chip circuitry. Each BIST engine consists of a mail control block, one address generation block having an address local control block and one or more address data generation blocks and one data generation block having a data local control block and one or more data generation blocks. The local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks. The main control block controls the operation of the local address and the data control blocks to provide desired testing, accessing and monitoring of the on-chip memory arrays.
The conventional methods and systems as discussed above do not overcome all the existing problems encountered in the field of chip testing like, requirement of a larger area, inability to test memories at-speed with a shared BIST, inability of a shared BIST in testing memories placed relatively far in the chip, etc.